The subject matter of the present application relates to microelectronic assemblies, e.g., microelectronic packages that include one or more semiconductor chips having active devices thereon, and more particularly to a microelectronic package design for more simplified power plane element routing.
Microelectronic elements, e.g., semiconductor chips, are thin, flat elements that can incorporate integrated circuits including active semiconductor devices such as transistors, diodes, etc., and wiring that provides electrical interconnections. Semiconductor chips may also or alternatively include passive devices such as capacitors, inductors or resistors. In particular constructions, a microelectronic element can include one or more semiconductor chips having an encapsulant on one or more surfaces thereof and having electrically conductive elements electrically connected with contacts of the one or more semiconductor chips, the contacts being exposed at a surface of the microelectronic element.
Semiconductor chips containing memory storage arrays, particularly dynamic random access memory chips (DRAMs) and flash memory chips are commonly packaged in single- or multiple-chip packages and assemblies. Each package has many electrical connections for carrying signals, power and ground between terminals and the chips therein. The electrical connections can include different kinds of conductors such as horizontal conductors, e.g., traces, beam leads, etc., that extend in a horizontal direction relative to a contact-bearing surface of a chip, vertical conductors such as vias, which extend in a vertical direction relative to the surface of the chip, and wire bonds that extend in both horizontal and vertical directions relative to the surface of the chip.
Conventional microelectronic packages can incorporate a microelectronic element that is configured to predominantly provide memory storage array function, i.e., a microelectronic element that embodies a greater number of active devices to provide memory storage array function than any other function. The microelectronic element may be or include a DRAM chip, or a stacked electrically interconnected assembly of such semiconductor chips. Typically, all of the terminals of such package are placed in sets of columns adjacent to one or more peripheral edges of a package substrate to which the microelectronic element is mounted.
Multiple power plane elements are increasingly common in modern system-on-a-chip (“SoC”) chips and packages, and in memory chip packages. For example, LPDDR3 mobile DRAM packages have four power supplies. For mobile applications, it is frequently desirable to have package substrates and circuit panels that have as small of a surface area as possible. There may be very limited space in package substrates and circuit panels for power plane elements, so it is increasingly important that the substrate and circuit panel area be used efficiently.
In light of the foregoing, certain improvements can be made to microelectronic packages to regulate the delivery of power to a microelectronic element, e.g., semiconductor chip, therein in order to improve electrical performance, particularly in assemblies that include such packages and a circuit panel to which such packages can be mounted and electrically interconnected with one another.